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product specifications oct 12, 2001 revision 0.54 u ltra c hip the coolest lcd driver. ever!! 65x102 matrix lcd controller-driver h igh -v oltage m ixed -s ignal ic
u ltra c hip high-voltage mixed-signal ic ?2000 2 product specifications
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 1 UC1602I single-chip, ultra-low power passive matrix lcd controller-driver i ntroduction UC1602I is an advanced high-voltage mixed- signal cmos ic, especially designed for the display needs of ultra-low power hand-held devices. in addition to low power column and row drivers, these ics contain all necessary circuits for high-v lcd power supply, bias voltage generation, timing generation and graphics data memory. advanced circuit design techniques are employed to minimize ex ternal component counts and reduce connector size while achieving extremely low power consumption. m ain a pplications ? cellular phones or smart phones ? pagers or other battery operated messaging devices ? battery powered portable instruments f eature h ighlights ? supports i 2 c 2-wire serial interface and 8- bit parallel bus interface. ? ultra-low power lcd controller-driver with built-in display ram and timing generator to support compact lcd module using as few as 5 pins. ? v dd2/3 voltage range: 2.4v ~ 3.3v v dd1 voltage range: 1.8v ~ 3.3v lcd v op range: 4.5v ~ 10.5v ? 6x, built-in self-configuring, charge pump allows the use of low v dd while produce high v lcd for driving lcd. ? on-chip charge pump pumping capacitors requires only 3 external capacitors. ? two multiplexing rates: 1/65, 1/49. ? four temperature compensations. ? support both high speed parallel interfaces and compact serial interfaces. ? flexible data addressing/mapping schemes to support wide ranges of software models and lcd layout placements. p ower c onsumption conditions symbol v dd : v lcd pump display pattern lcd loading typ. max. unit 2.7v : 8.5v 4x blank 95 2.7v : 8.5v 4x checker 105 2.4v : 8.5v 5x blank 110 2.4v : 8.5v 5x checker 65x102, 12nf panel $ 122 2.7v : 8.5v 4x blank/checker 65 2.4v : 8.5v 5x blank/checker no load 70 i dd(tot) sleep mode (display off) n/a 0.2 1 a $ lcd panel capacitance estimated when displaying checker pattern.
u ltra c hip high-voltage mixed-signal ic ?2000 2 product specifications o rdering i nformation nomenclature description UC1602I-pp-m pp: packaging gu: gold bumped, face up gd: gold bumped, face down f n : type n tcp film part number memory drivers mux rate supported versions UC1602I 65 x 102 65 com x 102 seg 1/65, 1/49 g general notes a pplication i nformation for improved readability, the specification contains many appl ication data points. when application information is given, it is advisory and does not form part of the specification for the device. b are d ie d isclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of ultrachip?s delivery. there is no post waffle saw/pack testing performed on individual die. although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, ultrachip has no control of third party procedures in the handli ng, packing or assembly of the die. accordingly, it is the responsibility of the customer to test and quality their application in which the die is to be used. ultrachip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. l ife s upport a pplications these devices are not designed for use in life support appli ances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. custom er using or selling these products for use in such applications do so at their own risk.
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 3 b lock d iagram row drivers column drivers power-on & reset control row address generator clock & timing gen. host interface control & status register command column address generator display data ram display data latches level shifters level shifter v lcd & bias generator page address generator data ram i/o buffer c b2 c b1 c lcd
u ltra c hip high-voltage mixed-signal ic ?2000 4 product specifications p in d escription name type pins description m ain p ower s upply v dd1 v dd2 v dd3 pwr v dd1 supplies for display data ram and digital logic, v dd2 supplies for v lcd /v b generator, v dd3 supplies for v ref and other analog circuits. v dd2 /v dd3 should be connected to the same power source. but v dd1 can be connected to a source voltage no higher than v dd2 /v dd3 . in cog applications, always use separate ito traces for v dd1 , v dd2 and v dd3 to reduce noise coupling. v ss v ss2 gnd ground. in cog applications, use separate ito traces to connect v ss and v ss2 to the separate gnd pins or to the shared gnd pin and minimize both ito resistance. lcd p ower s upply v b1+ v b1? v b0? v b0+ pwr lcd offset voltages. connect two c b capacitors between v b+ to v b0+ and v b0? to v b? . for optimum operation resul t, minimize the ito trace resistance of these nodes. place c b1 and c b0 on the fpc or cof to r educe i/o pin count by 4. v lcd-in v lcd-out pwr main lcd power supply. when internal v lcd is used, connect these pins together. when external v lcd source is used, connect external v lcd source to v lcd-in pins and leave v lcd-out pins open. a by-pass capacitor c l should be connected between v lcd and v ss2 . minimize the ito trace resistance in cog applications. n ote ? recommended capacitor values: c b : 150~500x lcd load capacitance or 1.0uf (v br > 3v), whichever is higher. c l : 20~50x lcd load capacitance or 0.2uf (v br > v lcd +1v), whichever is higher. name i/o pins description lcd d rive o utput ( up to 198 pins ) c0, ~ c101 hv lcd column driver outputs. support up to 102 columns. leave unused drivers open-circuit. ric hv lcd icon driver outputs. ric has two pads. these two pads are used to drive icons. leave unused drivers open-circuit. r1, r3, ... r63 r2, r4, ? hv lcd row driver outputs. support up to 64 rows. drivers for even and odd row are group into two separate groups along the two sides of the ic. leave unused drivers open-circuit.
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 5 name i/o pins description r64
u ltra c hip high-voltage mixed-signal ic ?2000 6 product specifications name type pins description c onfiguration p ins ps[1:0] c parallel/serial. serial modes: ?ll?: serial (s 8) ?lh?: 2-wire serial (i 2 c) parallel modes: ?hl?: 8080 ?hh?: 6800 v dd1 s for configuration purpose t est p ins tp3 i test control. connect to gnd. tp[2:0] i test control. leave these pins open during normal use. tst[3:1] i/o test i/o pins. leav e these pins open during normal use. h ost i nterface v dd1 s use for configuration purpose. cs0/a0 cs1/a1 i chip select or chip address. in parallel mode and s8 mode, chip is selected when cs0=?l? and cs1=?h?. in i 2 c mode, a[1:0] specifies bit 3~2 of UC1602I?s device address. when the chip is not selected , d[7:0] will be high impedance. rst i when rst=?l?, all control registers are re-initialized by their default states and/or by their pin co nfigurations if applicable. when rst is not used, connect the pin to v dd1 . cd i select control data or display data for read/write operation. cd pin is not used in i 2 c modes, connect it to v dd or v ss. ?l?: control data ?h?: display data wr0 wr1 i wr[1:0] controls the r ead/write operation of the host interface. in parallel mode, wr[1:0] meaning d epends on whether the interface is in the 6800 mode or the 8080 mode. in serial interface modes, these tw o pins are not used. connect to v ss . d0~d7 i/o bi-directional bus for both serial and parallel host interfaces. in s8 mode, connect unused pins to v dd or v ss . in i2c mode, connect d[1:0] to sck, and d[5:2] to sda, and d[7:6] to v dd or v ss . ps=1x ps=0x d0 d0 sck d1 d1 d2 d2 d3 d3 sda d4 d4 d5 d5 d6 d6 - d7 d7 - in i 2 c mode, sda and sck are in open-drain mode. pull up resistors are required on the bus. in cog applications, be careful to control ito trace resistance, as it will affect effective output level of sda. n ote ? unless otherwise specified, connect all u nused input pins and control pins to v ss .
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 7 c ontrol r egisters UC1602I contains registers which controls the ch ip operation. these registers can be modified by commands. the commands supported by UC1602I are described in the next section. name: the symbolic reference of the register byte. note that, some symbol names refers to collection of bits (flags) within one register byte. default: value after power-up-reset and system-reset . ?pin? means default value depends on the c onnection of associated configuration pin(s). name bits default description mr 1 1h multiplexing rate: number of pixel rows plus icon row. 0: 49 1: 65 sl 6 0h start line. mapping from row0 to display data ram. cr 8 0h return column address. ca 8 0h display data ram column address (used in host to display data ram access) pa 4 0h display data ram page address (used in host to display data ram access) br 2 2h bias ratio. the ratio between v lcd and v d . tc 2 0h temperature compensation (per o c). 00: 0.0% 01: -0.05% 10: -0.1% 11: -0.2% gn 2 3h gain = v d / v pm pm 6 10h electronic potential meter to generate v pm from v ref om 2 0 operating modes 10: sleep 11: normal 01: (not used) 00: reset bz 1 ? busy with internal processes (reset, changing mode, etc.) ok for display ram read/write access. rs 1 reset in progress, host interface not ready pc 3 07h power control. pc[0] 0: lcd load < 12nf 1: lcd load > 12nf pc[2:1] 00: external v lcd 01: 4x pump 10: 5x pump 11: 6x pump apc0 8 6ch advanced program control. default value should work fine.
u ltra c hip high-voltage mixed-signal ic ?2000 8 product specifications name bits default description dc 3 0h display control: dc[0]: pxv: pixels inverse dc[1]: apo: all pixels on dc[2]: de, display enable ac 4 0h address control: ac[0]: wa: automatic column/page wrap around ac[1]: reserved (always set to 0) ac[2]: pid: pa (page address) auto increment direction (l:+1 h:-1) ac[3]: cum: cursor update mode, when cum=1, ca increment on write only, wrap around suspended lc 4 0 0 0 0 lcd layout control: lc[0]: msf: msb first mapping option lc[1]: reserved (always set to 0) lc[2]: mx, mirror x (col umn sequence inversion) lc[3]: my, mirror y (row sequence inversion)
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 9 c ommands the following is a list of host commands support by uc1062i. c/d: 0: control, 1: data w/r: 0: write cycle, 1: read cycle # useful data bits ? don?t care command c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 action write data byte 1 0 ########write 1 byte @ pa/ca read data byte 1 1 ########read 1 byte @ pa/ca get status 0 1 bzmxders0000 get status summary set column address lsb 0 0 0000#### set ca[3:0]=d[3:0] set column address msb 0 0 0001#### set ca[7:4] =d[3:0] set mux rate & temperature compensation. 0 0 00100### set mr=d[2] set tc[1:0]=d[1:0] set power control 0 0 00101### set pc[2:0]=d[2:0] 0 0 001100 rr set adv. program control (double byte command) 0 0 ######## set apc[r][7:0]=d[7:0], where rr = 00, or 01 set start line 0 0 01###### set sl[5:0]=d[5:0] set v ref potential meter (double-byte command) 0 0 0 0 1 # 0 # 0 # 0 # 0 # 0 # 0 # 1 # set pm[5:0]=d[5:0] set gn[1:0]=d[7:6] set ram address control 0 0 10001### set ac[2:0]=d[2:0] set column mirroring 0 0 1010000# set lc[2]=d0 set all-pixel-on 0 0 1010010# set dc[1]=d0 set inverse display 0 0 1010011# set dc[0]=d0 set display on/off 0 0 1010111# set dc[2]=d0 set page address 0 0 1011#### set pa[3:0]=d[3:0] set lcd to ram mapping 0 0 1100##0# set lc[3:0]=d[3:0] set cursor update mode 0 0 11100000set ac[3]=1, cr=ca; system reset 0 0 11100010system reset s equence nop 0 0 11100011 no operation set lcd bias ratio 0 0 111010## set br[1:0]= d[1:0] set/reset cursor-update mode 0 0 1110111# set ac[3]=d0; if (d0) cr=ca else ca=cr; 0 0 111001 tt set test control (double byte command) 0 0 ######## for testing only. do not use. * other than commands listed above, all other bi t patterns result in nop (no operation).
u ltra c hip high-voltage mixed-signal ic ?2000 10 product specifications lcd v oltage s ettings m ultiplex r ates two multiplex rates are supported in UC1602I: 65 or 49. the default is 65 and it can be changed by programming. b ias s election bias ratio ( br ) is defined as the ratio between v lcd and v d , i.e. br = v lcd /v d , where v d is the seg data signal and its value is | v b1+ ? v b1? | the optimum bias ratio can be calculated by: 1 + mux UC1602I supports four bias ratios as below. br 0 1 2 3 bias ratio 6 7 8 9 table 2: br vs. mux rates br and mr can both be changed dynamically by software programming. v d g eneration v d is generated internally by uc106. the value of v d is determined by three control registers: gn (gain), pm (potential meter), tc (temperature compensation) with the following relationship: pm d v gain v = where v pm is the output of an internal electronic potential meter. the maximum value for v d depends on the value of v dd2 . at v dd2 = 2.4v, v d should be kept under 1.2v. the value of v pm is given by: ref pm v pm v + = 1200 600 the value of gain is controlled by gn[1:0]. their relationship is shown below: gn[1:0] 00 01 10 11 gain 1.35 1.49 1.64 1.81 table 3: gain vs. gn value v ref t emperature c ompensation v ref is a temperature compensated reference voltage. v ref increases automatically as ambient temperature cools down. four (4) different temp erature compensated v ref can be selected via pin wiring. the compensation coefficient is given by the following table: tc[1:0] 0 1 2 3 % per o c 0.0 ?0.05 ?0.10 ?0.20 table 4: temperature compensation for all tc values, v ref are normalized to 1.2v at 25 o c. v lcd s election v lcd may be supplied either by internal charge pump or by external power supply. the source of v lcd is controlled by pc[2:1]. when v lcd is generated internally its value has the following relationship with v d : d lcd v biasratio v = given v ref = 1.2v at 25 o c, v lcd becomes: 2 . 1 1200 600 + ? pm gain biasratio v lcd (1) when pm=0, then equation (1) becomes: 6 . 0 ? gain biasratio v lcd (1b) l oad d riving s trength uc106?s drivers and power supply circuits are designed to handle panel capacitance load of 25nf at v lcd =9v when v dd2 >= 2.4v. UC1602I load driving strength is sensitive to ito impedance of power supply circuits (v dd2 , v ss2 , v b0/b1 , v lcd .) be sure to minimize the resistance of these ito traces for cog applications. p ower s upply c onfiguration UC1602I has built-in charge pump with on-chip pumping capacitors. the number of pump stages used can be programmed by setting pc[2:1] register. make sure the chip is in reset mode before changing the value of pc[2:0]. given the same display quality, the lower the pc[2:1] setting the more efficient is UC1602I, but the weaker is the driving strength. in application, designer is recommended to verify the design with the highest setting first before trying lower settings to achieve better efficiency. due to the use of fully embedded power supply, built-in power ready detector, and drain circuit, there is no rigid power up or power down sequences for UC1602I controllers when using internal v lcd generator. on the other hand, caution must be exercised when external v lcd source is used. the general rule of thumb is to make sure display enable is
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 11 off before connecting or disconnecting external v lcd sources. lcd d isplay c ontrols c lock & t iming g enerator the nominal frequency of UC1602I built-in system clock is 166khz, the lcd refresh frequency is 80hz. all required components for the clock oscillator are built-in. no external parts are required. d river m odes row and column drivers can be in either idle mode or active mode, controlled by display enable flag (dc[2]). when column drivers are in idle mode, their outputs are high-impedance (open circuit). when row drivers are in idle mode, their outputs are connected to v ss . d river a rrangements the naming conventions are: r x (where x=1~64) refers to the row driver for the x-th row of pixels on the lcd panel; ric refers to the icon driver. row drivers are clustered into ?even row drivers? and ?odd row drivers?, along the two sides of the chip to enhance the symmetry of ito layout. the mapping of rx to lcd pixel rows is the same for all mr settings. when mr setting is not 11, leave unused row drivers open. d isplay c ontrols there are three display control flags in the control register dc: display enab le (de), all-pixel-on (apo) and inverse (pxv). de has the overriding effect over pxv and apo. d isplay e nable (de) display enable is controlled by the set display on command. when de is set to off (logic ?0?), both column and row drivers will become idle and the chip will put itself into sleep mode to conserve power. when the de is set to on, the chip will first exit from sleep mode by restoring the power (v lcd , v d etc.). when the power is restored, column and row drivers will become active. a ll p ixels o n (apo) when set, this flag will force all column drivers to output on signals, disregarding the data stored in the display buffer. this flag has no effect when display enable is off and it has no effect on data stored in ram. i nverse (pxv) when this flag set to on, column drivers will output the inverse of the value it received from the display buffer ram. this flag has no impact on data stored in ram.
u ltra c hip high-voltage mixed-signal ic ?2000 12 product specifications ram w/r eo r0 r1 r2 c0 c1 fig. 4 column and row driving waveform
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 13 h ost i nterface UC1602I series supports several parallel and serial host interface formats. bus bus type access 8080 r/w parallel 6800 r/w 4-wire (s8) w serial 2-wire (i 2 c) r/w table 5: host interfaces choices system designers can use either the 8-bit parallel bus to achieve the high data transfer rate, or use serial bus to create lcd modules with as few as 9-pin connectors. p arallel i nterface it is possible to interface UC1602I controllers directly to either an 8080-style mpu bus or a 6800-style mcu bus with the following connection. bus type wr0 wr1 8080 ___ ___ wr ___ __ rd 6800 _ _ r/w e table 6: mpu bus control signal interface the timing relationship between UC1602I internal control signal rd, wr and their associated bus actions are shown in the figure below. the generation of UC1602I internal bus control signals wr and rd is shown in the table below. bus type ___ ___ wr ___ __ rd 8080 wr0 wr1 6800 !(wr1 & !wr0) !(wr1 & wr0) table 7: wr and rd signal generation d isplay ram d ata t ransfer UC1602I display data ram (ram) read interface is implemented as a two-stage pipe-line. this architecture requires that, every time memory address is modified, either in parallel mode or serial mode, all three commands ( set ca-lsb, set ca-msb, set pa ) need to be issued, and a dummy read cycle need to be performed before the actual data can propagate through the pipe- line and be read from data port d[7:0]. there is no pipeline in write interface of ram, and the data is transferred directly from data bus buffer to ram. cd ___ wr __ rd d[7:0] write read bus holder column address l lsb d l d l+k c msb c lsb dummy d c d c+1 m msb m lsb d l d l+k dummy d c d c+1 l l+k l+k+1 c c+1 c+2 c+3 m figure 5: parallel interface & related internal signals
u ltra c hip high-voltage mixed-signal ic ?2000 14 product specifications s erial i nterface UC1602I supports two serial modes, 4-wire mode (ps=0), and 2-wire i 2 c mode (ps=1). the mode of interface is determined during power-up process by the value of ps[1:0]. 4- wier s erial i nterface (s8) only write operations are supported in 4-wire serial mode. pin cs[1-0] ar e used for chip select and bus cycle reset. pin cd is used to determine the content of the data been transferred. on each write cycle, 8 bits of data, msb first, are latched on eight (8) rising sck edges into an 8-bit data holder. if cd=0, the data byte will be decoded as command. if cd=1, this 8-bit will be treated as data and transferred to proper address in the display data ram at the rising edge of the last sck pulse. pin cd is examined when sck is pulled low for the lsb (d0) of each token. cs1/0 sdi sck cd d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 figure 6: 4-wire serial interface (s8) 2- wire s erial i nterface (i 2 c) when ps[1-0] is set to ?lh?, UC1602I is configured as a slave receiver/transmitter, for industry standard i 2 c serial interface. each UC1602I i 2 c interface sequence starts with a start condition (s) from the bus master, followed by a sequence header, containing a device address, the direction of transfer (rw, 0:write, 1:read) and mode of transfer (cd, 0:control, 1:data). in this mode, cs[1:0] become a[1:0] and are used to configure UC1602I?s device address. wr[1:0] and cd are not used and may be connected to gnd. write mode mpu mpu mpu mpu mpu ? ? ? ?? ? s0111 a 1 a 0 c d 0 a d 7 d 0 a ? ... a a p read mode mpu mpu mpu mpu mpu ? ? ? ?? ? s0111 a 1 a 0 c d 1 a d 7 d 0 a ? ... a np figure 7 : 2-wire interface protocol the direction and content of the bytes following each header byte are fixed for the sequence. to change the direction (r w) or the content type (c d), start a new interface sequence with a new header. after receiving the header, the UC1602I will send out an acknowledge signal (a). then, depends on the setting of the header, the transmitting device (either the bus master or UC1602I) will start placing data bits on the serial bus, msb to lsb, and the sequence will repeat until a stop signal (p, in write), or a not acknowledge (n, in read mode) is sent by the bus master. note that, for data read (cd=1), the first byte of data is dummy.
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 15 2- wire interface timing the 2-wire i 2 c interface is a bidirectional interface. in order to properly communicate between all i 2 c devices, certain timing protocols need to be satisfied. there are always master and slave devices on an i 2 c bus. the master device initiates an read or write action to the slav e device with an address. the selected slave device to the action transimitting or receiving data. without any action, the i 2 c bus are pulled high by two pull-up resistors. a master or slave device initiates or responds to an action by pulling down the bus. UC1602I is a slave i 2 c device. in idle mode, the both wires, sda and sck are pulled high. when the sda makes a high to low transition while sck remains high, this is the i 2 c start condition. when the sda makes a low to high transition while sck remain low, this is i 2 c stop condition. in between a start and stop condition, i 2 c transmits data bits by toggling sck while sda remains stable. these relations are shown in figure 8 . figure 8 . i 2 c bus sda and sck timing relation. each eight-bit of data is followed by an acknowledge pulse from the receiver as shown in figure 9 . the master device will generate an extra pulse during this time. it is the receiving device?s responsibility to generate this acknowledge pulse regardless of being a master or slave device. UC1602I generates an acknowledge pulse in the write mode. when the acknowledge pulse is high, UC1602I has received write instruction or data correctly. when the acknowledge pulse is low, UC1602I has not correctly received instruction and the master device needs to resend. figure 9 . i 2 c bus acknowledge pulse sda sck stop st art dat a 1 dat a 1 dat a 0 sck data transmitter data receiver s1 23 8 9 no-acknowled g e acknowledge
u ltra c hip high-voltage mixed-signal ic ?2000 16 product specifications s erial i nterface e xamples the table below shows an example of UC1602I to support a 9-pin (or 4-pin, if c lcd and c bx are mounted on fpc or cof) interface using i 2 c. hard wired comment rst=?h? use software reset exclusively. ca[1:0] =?xx? chip address sp=?01? UC1602I will power up and reset to i 2 c interface mode on fpc/cof comment v b0+ , v b0? v b1+ , v b1? connect to proper capacitors. these capacitors can be mounted on fpc as smd. interface comment sck connect to clock sda serial i/o v dd1 , v dd2 , v dd3 use three separate ito traces to one common node. v ss1 ,v ss2 use two separate ito to one common node. v lcd to v lcd bypass capacitor table 9: i 2 c interface example the table below shows an example of UC1602I to support a 11-pin (or 6-pin, if c lcd and c bx are mounted on fpc or cof), using s8, write-only interface mode and cd pin for bus control. hard wired comment rst=?h? use software reset exclusively. sp=?00? UC1602I will power up and reset to s8 interface mode sdo not used, connect to gnd on fpc/cof comment v b0+ , v b0? v b1+ , v b1? connect to two capacitors, mounted on fpc as smd. interface comment cs0 (or cs1) chip select cd control or display. sck connect to clock sda serial data in v dd1 , v dd2 , v dd3 use three separate ito traces to one common node. v ss1 ,v ss2 use two separate ito to one common node. v lcd to v lcd bypass capacitor table 10: s8 interface example
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 17 d isplay d ata ram d ata o rganization the display data is one bit per pixel and stored in a dual port static ram (ram, for display data ram). the ram size is 65x102. this array of data bits are further organized into pages of 8 bit slices to facilitate parallel bus interface. at the end of the graphics data, UC1602I contains an 1-bit wide page for icon data. when mirror x (mx, lc[2]) is off, the 1 st column of lcd pixels will correspond to the bits of the first byte of each page, the 2 nd column of lcd pixels correspond to the bits of the second byte of each page, etc. msb f irst or lsb f irst there are two options to map d[7:0] to ram, msb first (msf=1), or lsb first (msf=0), as illustrated below. d isplay d ata ram a ccess the memory used in UC1602I display data ram (ram) is a special purpose two port sram which allows asynchronous access to both its column and row data. thus, ram can be independently accessed both for host interface and for display operations. d isplay d ata ram a ddressing a host interface (hi) memory access operation starts with specifying page address (pa) and column address (ca) by issuing set page address and set column address commands. if wrap-around (wa, ac[0]) is off (0), ca will stop incrementing after reaching the end of page (102), and system programmers need to set the values of pa and ca explicitly. if wa is on (1), after ca has reached the end of page (ca=101), ca will be rest to 0 and pa will increment or decrement, depending on the setting of page increment direction (pid, ac[2]). when pa reaches the boundary of ram (i.e. pa = 0 or 7), pa will be wrapped around to the other end of ram and continue. i con d ata a ddressing the icon page is addressed by explicitly setting pa to 8 (the 9 th page). when addressing icon page, auto wrap-around will be suspended and ca will stop when ca reaches 102.
u ltra c hip high-voltage mixed-signal ic ?2000 18 product specifications line pa[3:0] 0 1 adderss sl=0 sl=16 sl=0 sl=0 sl=25 sl=25 d0 d7 00h r1 r49 r64 r48 r25 r9 d1 d6 01h r2 r50 r63 r47 r24 r8 d2 d5 02h r3 r51 r62 r46 r23 r7 d3 d4 03h r4 r52 r61 r45 r22 r6 d4 d3 04h r5 r53 r60 r44 r21 r5 d5 d2 05h r6 r54 r59 r43 r20 r4 d6 d1 06h r7 r55 r58 r42 r19 r3 d7 d0 07h r8 r56 r57 r41 r18 r2 d0 d7 08h r9 r57 r56 r40 r17 r1 d1 d6 09h r10 r58 r55 r39 r16 --- d2 d5 0ah r11 r59 r54 r38 r15 --- d3 d4 0bh r12 r60 r53 r37 r14 --- d4 d3 0ch r13 r61 r52 r36 r13 --- d5 d2 0dh r14 r62 r51 r35 r12 --- d6 d1 0eh r15 r63 r50 r34 r11 --- d7 d0 0fh r16 r64 r49 r33 r10 --- d0 d7 10h r17 r1 r48 r32 r9 --- d1 d6 11h r18 r2 r47 r31 r8 --- d2 d5 12h r19 r3 r46 r30 r7 --- d3 d4 13h r20 r4 r45 r29 r6 --- d4 d3 14h r21 r5 r44 r28 r5 --- d5 d2 15h r22 r6 r43 r27 r4 --- d6 d1 16h r23 r7 r42 r26 r3 --- d7 d0 17h r24 r8 r41 r25 r2 --- d0 d7 18h r25 r9 r40 r24 r1 --- d1 d6 19h r26 r10 r39 r23 r64 r48* d2 d5 1ah r27 r11 r38 r22 r63 r47 d3 d4 1bh r28 r12 r37 r21 r62 r46 d4 d3 1ch r29 r13 r36 r20 r61 r45 d5 d2 1dh r30 r14 r35 r19 r60 r44 d6 d1 1eh r31 r15 r34 r18 r59 r43 d7 d0 1fh r32 r16 r33 r17 r58 r42 d0 d7 20h r33 r17 r32 r16 r57 r41 d1 d6 21h r34 r18 r31 r15 r56 r40 d2 d5 22h r35 r19 r30 r14 r55 r39 d3 d4 23h r36 r20 r29 r13 r54 r38 d4 d3 24h r37 r21 r28 r12 r53 r37 d5 d2 25h r38 r22 r27 r11 r52 r36 d6 d1 26h r39 r23 r26 r10 r51 r35 d7 d0 27h r40 r24 r25 r9 r50 r34 d0 d7 28h r41 r25 r24 r8 r49 r33 d1 d6 29h r42 r26 r23 r7 r48 r32 d2 d5 2ah r43 r27 r22 r6 r47 r31 d3 d4 2bh r44 r28 r21 r5 r46 r30 d4 d3 2ch r45 r29 r20 r4 r45 r29 d5 d2 2dh r46 r30 r19 r3 r44 r28 d6 d1 2eh r47 r31 r18 r2 r43 r27 d7 d0 2fh r48 r32 r17 r1 r42 r26 d0 d7 30h r49 r33 r16 --- r41 r25 d1 d6 31h r50 r34 r15 --- r40 r24 d2 d5 32h r51 r35 r14 --- r39 r23 d3 d4 33h r52 r36 r13 --- r38 r22 d4 d3 34h r53 r37 r12 --- r37 r21 d5 d2 35h r54 r38 r11 --- r36 r20 d6 d1 36h r55 r39 r10 --- r35 r19 d7 d0 37h r56 r40 r9 --- r34 r18 d0 d7 38h r57 r41 r8 --- r33 r17 d1 d6 39h r58 r42 r7 --- r32 r16 d2 d5 3ah r59 r43 r6 --- r31 r15 d3 d4 3bh r60 r44 r5 --- r30 r14 d4 d3 3ch r61 r45 r4 --- r29 r13 d5 d2 3dh r62 r46 r3 --- r28 r12 d6 d1 3eh r63 r47 r2 --- r27 r11 d7 d0 3fh r64 r48 r1 --- r26 r10 1000 d0 d7 40h page 8 ricricricricricric 65 49 65 49 0 c0 c1 c2 c3 c4 c5 c6 c7 c97 c98 c99 c100 c101 1 c101 c100 c99 c98 c97 c96 c95 c94 c4 c3 c2 c1 c0 mx 0110 msf 0000 0001 0010 0011 0100 my=0 0111 page 0 page 1 page 2 page 3 page 4 0101 page 5 mux my=1 page 7 page 6
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 19 mx i mplementation column mirroring (mx) is implemented by selecting either (ca) or (101?ca) as the ram column address. changing mx affects the data written to the ram. since mx has no effect of the data already stored in ram, changing mx does not have immediate effect on the displayed pattern. to refresh the display, refresh the data stored in ram after setting mx. d isplay s canning during each field of display, depends on the setting of mr, row electrodes will be scanned in a fixed pattern at a rate of (80 x mux rate) rows/second . during each row period, the signal at the column drivers determine the on/off status of the row of pixels being scanned. r ow s canning icon data is always outputted via ric electrodes before the 1 st row of each field. it is then followed by scanning r1 through r m , where m may be 64, or 48 depends on the setting of mr. row electrode scanning orders are not affected by start line (sl) or mirror y (my, lc[3]). when my is 0, the effect of sl having a value k is to change the mapping of r0 to the k -th bit slice of data stored in display ram. visually, sl having a non-zero value is equivalent to scrolling lcd display up by sl rows. ram a ddress g eneration the mapping of the data store in the display sram and the scanning electrodes can be obtained by combining the fixed r m scanning sequence and the following ram address generation formula. during the display operation, the ram line address generation can be mathematically represented as following: for the 1 st line period of each field line = icon line (40h) for the 2 nd line period of each field line = sl otherwise line = mod( line +1, 64 ) where mod is the modular operator, and line is the bit slice line address of ram to be outputted to column drivers. line 0 corresponds to the first bit-slice of data in ram. the above line generation formula produce the ?loop around? effect as it effectively resets line to 0 when line+1 reaches 64 . effects such as page scrolling, page swapping can be emulated by changing sl dynamically. my i mplementation row mirroring (my) is implemented by reversing the mapping order between row electrodes and ram, i.e. the mathemat ical address generation formula becomes: for the 1 st line period of each field line = icon line (40h) for the 2 nd line period of each field line = mod( sl + mux-2 , 64 ) where mux = 65 or 49 otherwise line = mod( line-1 , 64 ) visually, the effect of my is equivalent to flipping the display upside down. the data stored in display ram is not affected by my.
u ltra c hip high-voltage mixed-signal ic ?2000 20 product specifications r eset & p ower m anagement t ypes of r eset UC1602I has two different types of reset: power-on-reset and system-reset . power-on-reset is performed right after v dd1 is connected to power. power-on-reset will first wait for about 12ms, depending on the time required for v dd to stabilize, and then trigger the system reset . system reset can also be activated by software command or by connecting rst pin to ground. in the following discussions, reset means system reset . r eset s tatus when UC1602I enters reset sequence: ? all non-pin configurable control registers will be reset to their default values. ? all pin configurable control registers will be reset according to their configuration pins. ? operation mode will be ?reset? ? system status bits rs and bz will stay as ?1? until the reset process is completed (for a duration of 3~5us). refer to control registers for details of control flags and their default values. refer to pin description for configuration pin definitions. when rs=1, only status read command is processed by uc106. all other commands are ignored. once entered reset mode, all control registers will be reset to their def ault values and capacitors will be discharged. in general it is necessary to set up control registers before transition out of the reset mode. o peration m odes UC1602I has three operating modes (om): reset, normal, sleep. mode reset sleep normal om 00 10 11 host interface active active active clock off off on lcd drivers off off on charge pump off off on draining circuit on off off table 11: operating modes c hanging o peration m ode two commands will initiate om transitions: set display enable , and system reset . action mode om set display enable ?on? normal 11 set display enable ?off? sleep 10 reset command rst_ pin pulled ?l? power on reset reset 00 table 12: om changes when dc[2] is modified by set display enable , om will be updated automatically. there is no other action required to enter power saving mode. for maximum energy utilization, sleep mode is designed to retain charges stored in external capacitors c b0 , c b1 and c lcd . to drain these capacitors, use reset command to activate the on-chip draining circuit. om changes are synchronized with the edges of UC1602I internal clock. to ensure consistent system states, wait at least 10us after system reset or set display enable command. e xiting p ower s ave m odes UC1602I contains internal logic to check whether v lcd and v d is ready before releasing row and column drivers from their off states. when exiting sleep mode and reset mode, column and row drivers will not be activated until UC1602I internal voltage sources are restored to their proper values. p ower -u p s equence UC1602I power-up sequence is simplified by built-in ?power ready? flags and by the automatic invocation of system-reset command after power-on-reset . system programmer are only required to wait 4~6 ms before starting to issue commands to uc106. no additional commands or waits are required between enabling of the charge pump, turning on the display drivers, writing to ram or any other commands. p ower -d own s equence to prevent the charge stored in capacitors c b+ , c b? , and c lcd from damaging the lcd when v dd is switched off, use reset mode to enable the built-in charge draining circuit to discharge these external capacitors. UC1602I draining resistance is 1k for both v lcd and v b+ . it is recommended to wait 3 x rc for
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 21 v lcd and 1.5 x rc for v b+ before allowing v dd to drop below 2v. for example, if c lcd is 1uf, then the draining time required for v lcd is 3~5ms. UC1602I will not drain v lcd when internal v lcd is not used. system designer should take care to make sure external v lcd source is properly drained off before turning off vdd. turn on vdd set lcd bias ratio (br) set gain (gn) set potential meter (pm) set display enable wait 4~6ms figure 12: reference power-up sequence turn off vdd reset command wait 3~5ms figure 13: reference power-down sequence
u ltra c hip high-voltage mixed-signal ic ?2000 22 product specifications s ample c ommand s equences the following table are host interface exam ples for various UC1602I operations. step sequences starting with the same number (such as 2a, 2b, 2c, ?) can be rear ranged without affecting the result. some optional steps have mutual dependen cies. such mutually-dependent optional steps need to be elected or skipped together as a group. c/d the type of the interface cycle. depending on the interface type (parallel or serial). this may be external pin (parallel a nd serial 8-bit), part of the bit st ream (serial 9-bit write) or the internal flag (serial 9-bit read). w/r the direction of data flow of the cycl e. it can be either write (0) or read (1). bz, om the status of these flags ? during ? the operation of the command. (opt.) optional item. p ower -u p sequence the only ? required ? command to initialize UC1602I is set display on . however, many other commands (such as set apo = 0/1, set lcd mapping ) and any of the nop bit patterns can be used for maximum software compatibility with other industry leading lcd controller-drivers. the following command sequence can be performed in parallel 8-bit, i 2 c or s8 modes. example 1: use system reset command. # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments ? ? ? ? ? ? ? ? ? ? power-on reset. v dd powering up. wait ~15ms for v dd to become steady. ?? 1 ? ? ? ? ? ? ? ? ? ? automatic system reset. ?? 1 0 1 d d d d ? ? ? ? (opt.) read status 00 0 (recommended) use ?read status? to make sure bz flag is 0 before issuing any other command. 0 0 1 0 1 0 1 0 0 0 (opt.) system reset 00 0 recommended. 0 0 1 1 1 0 1 0 # # (opt.) set bias ratio 00 0 0 0 0 0 1 0 0 # # # (opt.) set gain 00 0 0 ? 0 ? 1 ? 0 ? 0 # 0 # 0 # 0 # 0 # 1 # (opt.) set pm 00 0 0 0 0 0 1 0 1 # # # (opt.) set power control 00 0 if external v lcd is selected, activate the source here. 0 0 1 0 1 0 1 1 1 1 set display on 11 0 note: example 1 does not require the use of rst pi n and therefore is more appropriate for applications where compact connector size is critical.
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 23 example 2: use rst pin. # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments ? ? ? ? ? ? ? ? ? ? hold rst pin to ?l? until the external power is stable. ?? 1 0 1 d d d d ? ? ? ? (opt.) read status 00 0 recommended 0 0 1 1 1 0 0 0 1 0 (opt.) system reset 00 0 recommended 0 0 1 1 1 0 1 0 # # (opt.) set bias ratio 00 0 0 0 0 0 1 0 0 # # # (opt.) set gain 00 0 0 ? 0 ? 1 ? 0 ? 0 # 0 # 0 # 0 # 0 # 1 # (opt.) set pm 00 0 0 0 0 0 1 0 1 # # # (opt.) set power control 00 0 if external v lcd is selected, activate the source here. 0 0 1 0 1 0 1 1 1 1 set display on 11 0 p ower -d own s equences the following two command sequences can be performed in parallel, i 2 c or s8 modes. option 1: use system reset command. # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 0 0 1 1 1 0 0 0 1 0 system reset 00 1 ? ? ? ? ? ? ? ? ? ? (wait ~3ms) 00 0 draining c lcd , c b ? ? ? ? ? ? ? ? ? ? turn off v dd 00 0 note: option 1 does not require the use of rst pi n and therefore is more ap propriate for applications where compact connector size is critical. option 2: use rst pin. # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments ? ? ? ? ? ? ? ? ? ? hold rst to ?l?, wait ~3ms 00 1 draining c lcd , c b ? ? ? ? ? ? ? ? ? ? turn off v dd 00 0
u ltra c hip high-voltage mixed-signal ic ?2000 24 product specifications p repare t o a ccess d ata ram address control (register ac) flags and some lcd to sr am mapping (register lc) flags affect how data is stored into the display buffer sram => make proper ad justment to these two regi sters before writing data to UC1602I display buffer sram. these sequence can be performed in parallel 8-bit, i 2 c or s8 modes. these commands can be performed under any operating mode (om). # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 0 0 1 0 0 0 1 # # # (opt.) set address control ? 0 0 0 1 1 0 0 # # 0 # (opt.) set/clear lcd mapping control flags. ?0 d ata ram a ccess : w rite these sequence can be performed in parallel 8-bit, i 2 c or s8. these commands can be performed under any operating mode (om). # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 1 0 0 1 0 1 1 # # # # set page address ? 0 2 0 0 0 0 0 1 # # # # set column address msb ? 0 3 0 0 0 0 0 0 # # # # set column address lsb ? 0 4 1 0 # # # # # # # # write display data (repeat as appropriate) ?0 5 (return to 1 as necessary, repeat until complete) ?0 d ata ram a ccess : r ead for parallel interface and i 2 c modes, a dummy read cycle is required when a read data command follows immediately after a write cycle (eit her write data or write control). # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 1 x 0 1 0 1 1 # # # # write cycle (either data or control) ?0 for example: commands setting pa and/or ca. 2 1 1 ? ? ? ? ? ? ? ? dummy read cycle ? 0 3 1 1 # # # # # # # # read display data (repeat as appropriate) ?0
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 25 d ata ram a ccess : c ursor u pdate cursor can be used to support many flexible user interf ace designs. blinking curs or requires frequent update to a limited set of pixels. UC1602I cursor update mode is designed to facilitate such frequent data ram updates. under cursor update mode, both the wrap around (c a reset to 0, pa increment or decrement) and ca increment on read are temporary di sabled. these two features allow system designer to minimize the need to update ca and pa registers and allows on-chip ram to be used in read-modify-write style operations. e xample 1: c ursor u pdate with r ead -m odify -w rite , p arallel i nterface or i 2 c m ode # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 1 0 0 1 1 1 0 0 0 0 0 set cursor-update mode and set cr=ca ?0 cr tracks where ca should be restored later 1 1 ? ? ? ? ? ? ? ? dummy read cycle 2 1 1 # # # # # # # # read display data ? 0 ca unchanged 3 1 0 # # # # # # # # write display data ? 0 (return to 2 and repeat until the cursor is updated) ?0 ca will increment, but will not wrap around 4 0 0 1 1 1 0 1 1 1 0 clear cursor update mode ? 0 set ca=cr return to 1 for next cursor update cycle or continue ?0 e xample 2: c ursor u pdate w ithout r ead , a ll i nterface m odes # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 1 0 0 1 1 1 0 1 1 1 1 set cursor-update mode and set cr=ca ?0 cr remembers where ca should be restored later 2 1 0 # # # # # # # # write display data ? 0 3 (return to 2 and repeat until the cursor is updated) ?0 ca will increment but will not wrap around 4 0 0 1 1 1 0 1 1 1 0 clear cursor update mode ? 0 set ca=cr return to 1 for next cursor update cycle or continue ?0 e nable d isplay the following command sequence can be performed in all interface modes. # c/d w/r d7 d6 d5 d4 d3 d2 d1 d0 operation om bz comments 0 0 0 1 # # # # # # (opt.) set start line ? 0 0 0 1 0 1 0 0 1 0 # (opt.) set all-pixel-on ? 0 0 0 1 0 1 0 0 1 1 # (opt.) set inverse mode. ? 0 0 0 1 0 1 0 1 1 1 1 set display on 11 0 note: the order of these steps are not critical. however, for the smoothness of display effect, the above sequence is recommended.
u ltra c hip high-voltage mixed-signal ic ?2000 26 product specifications a bsolute m aximum r atings in accordance with iec134, note 1, 2 and 3. symbol parameter min. max. unit v dd1 logic supply voltage -0.3 +4 v v dd2 lcd generator supply voltage -0.3 +4 v v dd3 analog circuit supply voltage -0.3 +4 v v lcd lcd generated voltage -0.3 +12 v v in / v out any input/output -0.3 v dd + 0.3 v t opr operating temperature range -25 +85 o c t str storage temperature -50 +100 o c t j junction temperature +150 o c p ic total power dissipation 250 mw notes 1. v dd1 based on v ss1 = 0v. v lcd based on v ss2 = 0v. 2. stress outside values listed may cause permanent damages to the device.
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 27 s pecifications dc c haracteristics symbol parameter conditions min. typ. max. unit v dd1 digital supply voltage 2.4 3.7 v v dd2 supply for v lcd generation 2.4 3.7 v v lcd lcd driving voltage 4.5 10.5 v v b0 lcd bias voltage v v il input logic low 0.2vdd v v ih input logic high 0.8vdd v v ol output logic low 0.2vdd v v oh output logic high 0.8vdd v i il input leakage current 1 a i oz output leakage current a r 0(col.) column output impedance v lcd = 9.0v 2.4 4.0 k ? r 0(row) row output impedance v lcd = 9.0v 2.4 4.0 k ? f clk internal clock frequency 133 166 200 khz
u ltra c hip high-voltage mixed-signal ic ?2000 28 product specifications ac c haracteristics cd cs0, cs1 wr0, wr1 d[7:0] write d[7:0] read t as80 t ah80 t cy80 t ds80 t dh80 t od80 t acc80 t pwr80 , t pww80 0.8v dd 0.2v dd t hpw80 figure 21: parallel bus timing characteristics (for 8080 mcu) (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 25 50 ? ns t cy80 system cycle time 300 ? ns t pwr80 wr1 pulse width (read) 120 ? ns t pww80 wr0 pulse width (write) 60 ? ns t hpw80 wr0, wr1 high pulse width 60 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 40 15 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 10 140 100 ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as80 t ah80 cd address setup time address hold time 20 45 ? ns t cy80 system cycle time 166 ? ns t pwr80 wr1 pulse width (read) 75 ? ns t pww80 wr0 pulse width (write) 30 ? ns t hpw80 wr0, wr1 high pulse width 30 ? ns t ds80 t dh80 d0~d7 data setup time data hold time 30 10 ? ns t acc80 t od80 read access time output disable time c l = 100pf ? 10 65 45 ns
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 29 cd cs0, cs1 wr1 d[7:0] write d[7:0] read t as68 t ah68 t cy68 t ds68 t dh68 t od68 t acc68 t pwr68 , t pww68 0.8v dd 0.2v dd t lpw68 figure 22: parallel bus timing characteristics (for 6800 mcu) (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 25 50 ? ns t cy68 system cycle time 300 ? ns t pwr68 wr1 pulse width (read) 120 ? ns t pww68 pulse width (write) 60 ? ns t lpw68 low pulse width 60 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 40 15 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 10 140 100 ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t as68 t ah68 cd address setup time address hold time 20 45 ? ns t cy68 system cycle time 166 ? ns t pwr68 wr1 pulse width (read) 75 ? ns t pww68 pulse width (write) 30 ? ns t lpw68 low pulse width 30 ? ns t ds68 t dh68 d0~d7 data setup time data hold time 30 10 ? ns t acc68 t od68 read access time output disable time c l = 100pf ? 10 70 50 ns
u ltra c hip high-voltage mixed-signal ic ?2000 30 product specifications cs0 cs1 cd sck sdi (input) t chs8 t dss8 t dhs8 t css8 t cys8 0.8v dd 0.2v dd t wls8 t whs8 t cdss8 t cdhs8 figure 23: serial bus (s8 mode) timing characteristics (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t css8 t chs8 cs cs setup time cs hold time 150 150 ? ns t cdss8 t cdhs8 cd cd setup time cd hold time 15 10 ? ns t cys8 t whs8 t wls8 sck sck clock cycle sck high width sck low width 250 100 100 ? ns t dss8 t dhs8 sda data setup time data hold time 90 90 ? ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t css8 t chs8 cs cs setup time cs hold time 100 100 ? ns t cdss8 t cdhs8 cd cd setup time cd hold time 10 5 ? ns t cys8 t whs8 t wls8 sck sck clock cycle sck high width sck low width 200 75 75 ? ns t dss8 t dhs8 sda data setup time data hold time 50 50 ? ns
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 31 sck sdo (output) sdi (input) t ods9 t dss9 t dhs9 t cys9 0.8v dd 0.2v dd t wls9 t whs9 t acs9 t acs9 figure 24: serial bus (i 2 c mode) timing characteristics (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t cys9 t whs9 t wls9 sck serial i/o clock cycle sck high width sck low width ns t dss9 t dhs9 sda data setup time data hold time ns t acs9 t ods9 sda read access time output disable time c l = 100pf ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t cys9 t whs9 t wls9 sck serial i/o clock cycle sck high width sck low width ns t dss9 t dhs9 sda data setup time data hold time ns t acs9 t ods9 sda read access time output disable time c l = 100pf ns
u ltra c hip high-voltage mixed-signal ic ?2000 32 product specifications rst t rw figure 25: reset characteristics (vdd=2.4v to 3.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 1000 ? ns (vdd=3.0v to 4.0v, ta= ?30 to +85 o c) symbol signal description condition min. max. units t rw rst reset low pulse width 500 ? ns
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 33 p hysical d imensions
u ltra c hip high-voltage mixed-signal ic ?2000 34 product specifications # pin x y bx by 1 dummy1 -3500.7 447.0 100 51 2 r21 -3500.7 385.0 100 35 3 r23 -3500.7 330.0 100 35 4 r25 -3500.7 275.0 100 35 5 r27 -3500.7 220.0 100 35 6 r29 -3500.7 165.0 100 35 7 r31 -3500.7 110.0 100 35 8 r33 -3500.7 55.0 100 35 9 r35 -3500.7 0.0 100 35 10 r37 -3500.7 -55.0 100 35 11 r39 -3500.7 -110.0 100 35 12 r41 -3500.7 -165.0 100 35 13 r43 -3500.7 -220.0 100 35 14 r45 -3500.7 -275.0 100 35 15 r47 -3500.7 -330.0 100 35 16 r49 -3500.7 -385.0 100 35 17 dummy2 -3500.7 -447.0 100 51 18 r51 -3327.6 -420.5 35 100 19 r53 -3272.6 -420.5 35 100 20 r55 -3217.6 -420.5 35 100 21 r57 -3162.6 -420.5 35 100 22 r59 -3107.6 -420.5 35 100 23 r61 -3052.6 -420.5 35 100 24 r63 -2997.6 -420.5 35 100 25 ric -2942.6 -420.5 35 100 26 cs0 -2859.9 -440.5 50 80 27 cs1 -2789.9 -440.5 50 80 28 vdd1 -2719.9 -440.5 50 80 29 tp3 -2649.9 -440.5 50 80 30 rst -2579.9 -440.5 50 80 31 cd -2509.9 -440.5 50 80 32 wr0 -2439.9 -440.5 50 80 33 wr1 -2369.9 -440.5 50 80 34 vdd1 -2299.9 -440.5 50 80 35 d0 -2229.9 -440.5 50 80 36 d1 -2159.9 -440.5 50 80 37 d2 -2089.9 -440.5 50 80 38 d3 -2019.9 -440.5 50 80 39 d4 -1949.9 -440.5 50 80 40 d5 -1879.9 -440.5 50 80 41 d6 -1809.9 -440.5 50 80 42 d7 -1739.9 -440.5 50 80 43 vdd1 -1669.8 -440.5 50 80 44 vdd1 -1599.8 -440.5 50 80 45 vdd1 -1529.9 -440.5 50 80 # pin x y bx by 46 vdd2 -1389.8 -440.5 50 80 47 vdd2 -1319.8 -440.5 50 80 48 vdd2 -1249.8 -440.5 50 80 49 vdd2 -1179.9 -440.5 50 80 50 vdd3 -1039.9 -440.5 50 80 51 vss2 -622.6 -440.5 50 80 52 vss2 -552.6 -440.5 50 80 53 vss2 -482.6 -440.5 50 80 54 vss2 -412.6 -440.5 50 80 55 vss -342.6 -440.5 50 80 56 vss -272.6 -440.5 50 80 57 vss -202.6 -440.5 50 80 58 vss -132.6 -440.5 50 80 59 tst3 -62.6 -440.5 50 80 60 tst2 77.4 -440.5 50 80 61 tst1 217.4 -440.5 50 80 62 vb1+ 357.6 -440.5 50 80 63 vb1+ 427.6 -440.5 50 80 64 vb1+ 497.6 -440.5 50 80 65 ps0 637.6 -440.5 50 80 66 vdd1 777.6 -440.5 50 80 67 ps1 847.6 -440.5 50 80 68 vb1- 987.6 -440.5 50 80 69 vb1- 1057.6 -440.5 50 80 70 vb1- 1127.6 -440.5 50 80 71 tp2 1267.6 -440.5 50 80 72 tp1 1407.6 -440.5 50 80 73 tp0 1547.6 -440.5 50 80 74 vb0- 1688.6 -440.5 50 80 75 vb0- 1758.6 -440.5 50 80 76 vb0- 1828.6 -440.5 50 80 77 vb0- 1898.6 -440.5 50 80 78 vb0+ 2038.6 -440.5 50 80 79 vb0+ 2108.6 -440.5 50 80 80 vb0+ 2178.6 -440.5 50 80 81 vb0+ 2248.6 -440.5 50 80 82 vlcdout 2388.6 -440.5 50 80 83 vlcdin 2528.6 -440.5 50 80 84 vlcdout 2668.6 -440.5 50 80 85 vlcdin 2738.6 -440.5 50 80 86 vdd2 2808.6 -440.5 50 80 87 vdd2 2878.5 -440.5 50 80 88 r64 2942.6 -420.5 35 100 89 r62 2997.6 -420.5 35 100 90 r60 3052.6 -420.5 35 100
UC1602I 65x102 matrix lcd controller-drivers rev. 0.54 10/12/2001 35 # pin x y bx by 91 r58 3107.6 -420.5 35 100 92 r56 3162.6 -420.5 35 100 93 r54 3217.6 -420.5 35 100 94 r52 3272.6 -420.5 35 100 95 r50 3327.6 -420.5 35 100 96 dummy3 3500.7 -447.0 100 51 97 r48 3500.7 -385.0 100 35 98 r46 3500.7 -330.0 100 35 99 r44 3500.7 -275.0 100 35 100 r42 3500.7 -220.0 100 35 101 r40 3500.7 -165.0 100 35 102 r38 3500.7 -110.0 100 35 103 r36 3500.7 -55.0 100 35 104 r34 3500.7 0.0 100 35 105 r32 3500.7 55.0 100 35 106 r30 3500.7 110.0 100 35 107 r28 3500.7 165.0 100 35 108 r26 3500.7 220.0 100 35 109 r24 3500.7 275.0 100 35 110 r22 3500.7 330.0 100 35 111 r20 3500.7 385.0 100 35 112 dummy4 3500.7 447.0 100 51 113 r18 3327.4 420.5 35 100 114 r16 3272.4 420.5 35 100 115 r14 3217.4 420.5 35 100 116 r12 3162.4 420.5 35 100 117 r10 3107.4 420.5 35 100 118 r8 3052.4 420.5 35 100 119 r6 2997.4 420.5 35 100 120 r4 2942.4 420.5 35 100 121 r2 2887.4 420.5 35 100 122 ric 2832.4 420.5 35 100 123 c0 2777.4 420.5 35 100 124 c1 2722.4 420.5 35 100 125 c2 2667.4 420.5 35 100 126 c3 2612.4 420.5 35 100 127 c4 2557.4 420.5 35 100 128 c5 2502.4 420.5 35 100 129 c6 2447.4 420.5 35 100 130 c7 2392.4 420.5 35 100 131 c8 2337.4 420.5 35 100 132 c9 2282.4 420.5 35 100 133 c10 2227.4 420.5 35 100 134 c11 2172.4 420.5 35 100 135 c12 2117.4 420.5 35 100 # pin x y bx by 136 c13 2062.4 420.5 35 100 137 c14 2007.4 420.5 35 100 138 c15 1952.4 420.5 35 100 139 c16 1897.4 420.5 35 100 140 c17 1842.4 420.5 35 100 141 c18 1787.4 420.5 35 100 142 c19 1732.4 420.5 35 100 143 c20 1677.4 420.5 35 100 144 c21 1622.4 420.5 35 100 145 c22 1567.4 420.5 35 100 146 c23 1512.4 420.5 35 100 147 c24 1457.4 420.5 35 100 148 c25 1402.4 420.5 35 100 149 c26 1347.4 420.5 35 100 150 c27 1292.4 420.5 35 100 151 c28 1237.4 420.5 35 100 152 c29 1182.4 420.5 35 100 153 c30 1127.4 420.5 35 100 154 c31 1072.4 420.5 35 100 155 c32 1017.4 420.5 35 100 156 c33 962.4 420.5 35 100 157 c34 907.4 420.5 35 100 158 c35 852.4 420.5 35 100 159 c36 797.4 420.5 35 100 160 c37 742.4 420.5 35 100 161 c38 687.4 420.5 35 100 162 c39 632.4 420.5 35 100 163 c40 577.4 420.5 35 100 164 c41 522.4 420.5 35 100 165 c42 467.4 420.5 35 100 166 c43 412.4 420.5 35 100 167 c44 357.4 420.5 35 100 168 c45 302.4 420.5 35 100 169 c46 247.4 420.5 35 100 170 c47 192.4 420.5 35 100 171 c48 137.4 420.5 35 100 172 c49 82.4 420.5 35 100 173 c50 27.4 420.5 35 100 174 c51 -27.6 420.5 35 100 175 c52 -82.6 420.5 35 100 176 c53 -137.6 420.5 35 100 177 c54 -192.6 420.5 35 100 178 c55 -247.6 420.5 35 100 179 c56 -302.6 420.5 35 100 180 c57 -357.6 420.5 35 100
u ltra c hip high-voltage mixed-signal ic ?2000 36 product specifications # pin x y bx by 181 c58 -412.6 420.5 35 100 182 c59 -467.6 420.5 35 100 183 c60 -522.6 420.5 35 100 184 c61 -577.6 420.5 35 100 185 c62 -632.6 420.5 35 100 186 c63 -687.6 420.5 35 100 187 c64 -742.6 420.5 35 100 188 c65 -797.6 420.5 35 100 189 c66 -852.6 420.5 35 100 190 c67 -907.6 420.5 35 100 191 c68 -962.6 420.5 35 100 192 c69 -1017.6 420.5 35 100 193 c70 -1072.6 420.5 35 100 194 c71 -1127.6 420.5 35 100 195 c72 -1182.6 420.5 35 100 196 c73 -1237.6 420.5 35 100 197 c74 -1292.6 420.5 35 100 198 c75 -1347.6 420.5 35 100 199 c76 -1402.6 420.5 35 100 200 c77 -1457.6 420.5 35 100 201 c78 -1512.6 420.5 35 100 202 c79 -1567.6 420.5 35 100 203 c80 -1622.6 420.5 35 100 204 c81 -1677.6 420.5 35 100 205 c82 -1732.6 420.5 35 100 206 c83 -1787.6 420.5 35 100 207 c84 -1842.6 420.5 35 100 208 c85 -1897.6 420.5 35 100 209 c86 -1952.6 420.5 35 100 210 c87 -2007.6 420.5 35 100 211 c88 -2062.6 420.5 35 100 212 c89 -2117.6 420.5 35 100 213 c90 -2172.6 420.5 35 100 214 c91 -2227.6 420.5 35 100 215 c92 -2282.6 420.5 35 100 216 c93 -2337.6 420.5 35 100 217 c94 -2392.6 420.5 35 100 218 c95 -2447.6 420.5 35 100 219 c96 -2502.6 420.5 35 100 220 c97 -2557.6 420.5 35 100 221 c98 -2612.6 420.5 35 100 222 c99 -2667.6 420.5 35 100 223 c100 -2722.6 420.5 35 100 224 c101 -2777.6 420.5 35 100 225 r1 -2832.6 420.5 35 100 226 r3 -2887.6 420.5 35 100 # pin x y bx by 227 r5 -2942.6 420.5 35 100 228 r7 -2997.6 420.5 35 100 229 r9 -3052.6 420.5 35 100 230 r11 -3107.6 420.5 35 100 231 r13 -3162.6 420.5 35 100 232 r15 -3217.6 420.5 35 100 233 r17 -3272.6 420.5 35 100 234 r19 -3327.6 420.5 35 100 g old b ump s ummary type w l spacing hv 35 100 20 lv/pwr 50 80 20 * w refers to the side along the edge of chip. * all numbers in um. a lignment m arks shape x y size circle 196 43 45 circle 6975 43 45

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